Invalidity Analysis — US9000536 (public record)

Full Analysis

Invalidity Analysis

Invalidity Analysis — US9000536 (public record)

Patent No.: US9000536
Generated: Aug 28, 2026

Generated on a public patent — no confidential disclosure involved.

Overview & Grounds

About This Analysis

Prior-art invalidity analysis of a published / issued patent, prepared as attorney work product for your review and action. For attorney review — not a legal opinion, and not a validity determination; verify every reference, date, and quotation. This analysis charts the strongest prior-art references element-by-element against the target's independent claims and presents ranked candidate §102 anticipation and §103 obviousness grounds — each with a strength assessment, its weakest link, and the patentee's likely counterarguments. It applies a deterministic priority-date filter: a reference dated on or after the target's priority date is NOT prior art and is excluded from the grounds. Nothing confidential was analyzed — the input is a published patent, and the prior-art searches used the target patent's own public language.

Target patent: US9000536
Title: Fin field effect transistor having a highly doped region
Priority date (as extracted): 2013-06-28

Ranked Invalidity Grounds

For attorney review — not a legal opinion, not a validity determination. The provided IS4 charts confirm no eligible reference anticipates any independent claim under §102: the distinctive limitation across claims 1, 9, and 15 — a HIGHLY DOPED region (higher than the fin bulk) running along MULTIPLE outer edges (top + sidewalls) of the channel, positioned vertically and laterally between the channel and the gate dielectric (i.e., under the gate) — is absent from every single reference. US6525403B2 discloses a higher-doped 'third impurity region' but only in the fin TOP surface; US7202517B2 discloses a surface region wrapping the fin edges but doped LOWER than the bulk (retrograde), which arguably teaches away from the claimed higher-doped edge region; US7348284B2 discloses a layer conformally wrapping the top and both sidewalls of a fin between the fin and the gate dielectric (the claimed inverted-'U' geometry) but that layer is a strained-SiGe channel, not a region differentially doped higher than the bulk. The strongest candidate grounds are therefore §103 combinations pairing US6525403B2's higher-doped-top-surface teaching with US7348284B2's fin-wrapping surface-layer geometry; these are moderate-to-weak because the motivation to make the wrapping layer HIGHLY doped (and non-conductive, for effective-oxide-thickness/hot-carrier purposes) may draw impermissibly on the target's own disclosure, and the retrograde-doping reference presents a genuine teaching-away problem. Dependent limitations reciting dielectric materials, STI isolation, and doping species/ranges are broadly disclosed across the corpus, but they do not cure the central missing element in the independent claims.

Candidate grounds for attorney evaluation, ranked strongest-first — not a validity determination. Confirm every reference date and quotation before relying on a ground. Charts exist for independent claims only; dependent coverage is asserted, not charted.

#	Ground	References	Claims	Strength	Key weakness
1	§103 · Obviousness	US6525403B2, US7348284B2	1, 2, 3, 4, 5, 6, 9, 10, 11, 12, 14, 15, 17, 18, 19	MODERATE	US7348284B2's fin-wrapping layer is a strained-SiGe CHANNEL layer, not a region doped higher than the bulk; the motivation to make that conformal wrapping region HIGHLY doped (and non-conductive, to increase effective oxide thickness) is the precise inventive insight of the target and may be supplied only by hindsight from the target's own disclosure. US6525403B2's higher-doped region is expressly confined to the top surface, so the 'multiple outer edges' arrangement is not disclosed by either reference standing alone.
2	§103 · Obviousness	US6525403B2, US7348284B2, US7288823B2, US20130026575A1	13, 19, 20	MODERATE	These references cure only the dependent-claim add-ons; the ground rises or falls with the rank-1 combination's ability to reach the independent claims, which is itself only moderate due to the missing 'highly-doped multiple-edge region' element.
3	§103 · Obviousness	US7202517B2, US6525403B2	1, 4, 7, 9, 12, 14, 15, 17	WEAK	US7202517B2 is a textbook teaching-away reference: its entire stated purpose is that the surface region be LOWLY doped to reduce ionized-impurity scattering and preserve carrier mobility ('high surface mobility of the carriers is obtained because ionized impurity scattering is reduced'). Reversing that to a highly-doped surface would defeat the reference's intended purpose and change its principle of operation (MPEP §§ 2143.01, 2145).
4	§103 · Obviousness	US20110272763A1, US6525403B2, US7348284B2	9, 15, 16, 18	WEAK	US20110272763A1 expressly forms its resistance region OUTSIDE the gate, in the extension/upper portion 'except a portion of the fin-shaped semiconductor region located beneath the gate electrode' — the opposite location from the target's requirement that the region sit under the gate between the channel and gate dielectric. Its region is also confined to the upper (top) portion, not wrapping the sidewalls.

§103 · ObviousnessMODERATEMPEP §2143(C)

US6525403B2US6525403B2US7348284B2US7348284B2

Independent claims charted: 1, 9, 15 · dependent coverage asserted, not charted: 2, 3, 4, 5, 6, 10, 11, 12, 14, 17, 18, 19

US6525403B2 supplies the generic fin FET (semiconductor projection protruding from substrate, gate over side/top surfaces with interposed gate insulating film, source/drain on both sides — claims 1, 7, 16) plus the concept of a surface region doped HIGHER than the fin body. US7348284B2 supplies the structural geometry of a layer wrapping the top surface and both sidewalls of the fin, nested inside the overlying gate dielectric (FIGS. 1E-1F: 'The dielectric layer 409 covers the top surface and two opposing sidewalls of the tri-gate fin 407 with the strained Si1-yGey layer 408'), and the down-to-base vertical extent used for claim 9's element 8 and claim 15's top-and-sidewall region. Combined, the references would render obvious a highly-doped region located along multiple outer edges of the channel, arranged vertically and laterally between channel and gate dielectric (claims 1, 14, 15). US7348284B2 also supplies dependent limitations: boron dopant species (claims 6/11 — p-type boron S/D) and doping ranges overlapping 1E18-1E20 cm-3 (claims 5/10 — 'concentration of the n-type dopants is in the approximate range of 2×10^16 cm−3 to 2×10^19 cm−3'), and gate-dielectric materials ZrO2/HfO2 (claim 19).

Motivation to combine

Both references are in the same field of endeavor (non-planar/tri-gate fin transistors). US6525403B2 teaches that a fin can carry a higher-doped surface region (claims 2/5: 'a third impurity region ... formed in the top surface of the semiconductor projection, the third impurity region being higher in doping level than the semiconductor layer of the semiconductor projection'). US7348284B2 teaches forming a thin conformal surface layer that 'covers the top surface and two opposing sidewalls of the tri-gate fin' with the gate dielectric then formed over that layer — the very inverted-'U' geometry recited in claims 2-3. A PHOSITA seeking uniform gate control around all three exposed fin faces would have applied US7348284B2's known conformal-wrapping technique to US6525403B2's higher-doped surface region so that the higher-doped region runs along the top AND sidewalls rather than the top alone, a predictable extension of a known surface-region technique to a device ready for improvement, with a reasonable expectation of success because conformal fin surface layers were routinely formed (epitaxy/implant) in this art.

⚠ Key weakness US7348284B2's fin-wrapping layer is a strained-SiGe CHANNEL layer, not a region doped higher than the bulk; the motivation to make that conformal wrapping region HIGHLY doped (and non-conductive, to increase effective oxide thickness) is the precise inventive insight of the target and may be supplied only by hindsight from the target's own disclosure. US6525403B2's higher-doped region is expressly confined to the top surface, so the 'multiple outer edges' arrangement is not disclosed by either reference standing alone.

Anticipated counterarguments

1.Neither reference discloses or suggests a surface region that is both wrapped around multiple fin edges AND doped higher than the bulk; US7348284B2's wrapping layer is a channel, and US6525403B2's higher-doped region is top-surface-only — the combination reconstructs the claim only with hindsight (MPEP § 2143.01).
2.US7348284B2's strained-SiGe layer functions as the mobility-enhancing channel; making it a 'non-conductive' highly doped region (claim 8) that carries little current would render it unsatisfactory for its intended purpose and change its principle of operation.
3.The full specification and figures of US6525403B2 were not provided (mappings rest on the claims text only), so the 'protruding second fin' gate geometry and perpendicular orientation are UNVERIFIED.

§103 · ObviousnessMODERATEMPEP §2143(A)

US6525403B2US6525403B2US7348284B2US7348284B2US7288823B2US7288823B2US20130026575A1US20130026575A1

dependent coverage asserted, not charted: 13, 19, 20

Assuming the rank-1 combination reaches the independent claims, claim 13/20's 'sections of dielectric material extending along the first direction and separating the first fin ... from additional fins' is disclosed by US7288823B2 ('a device isolation insulating film pattern that fills device isolation trench regions'; STI films separating fins) and US6525403B2's device-isolation insulating films. Claim 19's gate-dielectric list (SiO2, HfO2, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2) is disclosed by US20130026575A1 ('SiO2, SiON, or a metal oxide such as ... HfO2, HfSiOx ... Ta2O5, TiO2 ...') and US7348284B2 (ZrO2, HfO2).

Motivation to combine

The dependent limitations reciting inter-fin dielectric isolation and high-k gate-dielectric material selection are conventional and were combined routinely with fin transistors. US7288823B2 discloses STI 'device isolation insulating film' sections separating fins running along the fin direction; US20130026575A1 and US7348284B2 disclose the enumerated gate-dielectric materials. A PHOSITA building the fin device of the rank-1 combination would incorporate standard STI isolation between adjacent fins and select a conventional high-k gate dielectric, yielding predictable results.

⚠ Key weakness These references cure only the dependent-claim add-ons; the ground rises or falls with the rank-1 combination's ability to reach the independent claims, which is itself only moderate due to the missing 'highly-doped multiple-edge region' element.

Anticipated counterarguments

1.The dependent limitations are conceded to be conventional, but conventional add-ons cannot supply the novel highly-doped-edge structure that the independent claims require and that no reference discloses.
2.US7288823B2's teaching is directed to a thick NON-channel gate oxide and a top hard-mask double-gate scheme (a different structural approach) and does not disclose the claimed highly-doped region, so importing only its STI teaching risks improper piecemeal selection (MPEP § 2141.02).

§103 · ObviousnessWEAKMPEP §2143(B)

US7202517B2US7202517B2US6525403B2US6525403B2

Independent claims charted: 1, 9, 15 · dependent coverage asserted, not charted: 4, 7, 12, 14, 17

US7202517B2 discloses the generic FinFET architecture and, critically, a surface region running along the top and sidewalls of the fin between the fin bulk and the gate — the geometric location claim 1/15 requires for the highly-doped region. Substituting US6525403B2's teaching that the surface region be doped higher than the bulk (rather than US7202517B2's lower retrograde doping) would arrive at a highly-doped edge region between channel and gate dielectric (claims 1, 7, 14, 15), with sidewalls planar with the underlying fin (claims 4, 12, 17).

Motivation to combine

US7202517B2 establishes that a FinFET fin can have a distinct surface region wrapping the fin edges with a doping level different from the bulk ('the surface region is located between the gate structure and two sidewalls of the bulk region ... the bulk region has a first dopant concentration level and the surface region has a second dopant concentration level'). US6525403B2 teaches that a fin surface region can be doped HIGHER than the fin body. A PHOSITA aware that a wrapping surface region's doping can be tuned relative to the bulk could, as a simple substitution, select a higher (rather than lower) surface doping to obtain a predictable threshold/edge-control effect.

Element coverage — claim 1

A Fin field effect transistor (FinFET) device: US7202517B2 · US6525403B2
a first fin of semiconducting material protruding from a semiconductor substrate: US7202517B2 · US6525403B2
the first fin of semiconducting material comprises a channel region: US7202517B2 · US6525403B2
the first fin of semiconducting material comprises a highly doped region located along multiple outer edges of the channel region: US6525403B2
a gate region protruding from the semiconductor substrate as a second fin that overlies the first fin of semiconducting material: US7202517B2 · US6525403B2
a gate dielectric layer located between the highly doped region and the gate region: US7202517B2 · US6525403B2
the highly doped region is vertically and laterally arranged between the channel region and the gate dielectric layer: not shown

Element coverage — claim 9

A Fin field effect transistor (FinFET) device: US7202517B2 · US6525403B2
a planar substrate comprising a semiconductor material: US7202517B2 · US6525403B2
a channel region comprising a first fin of semiconductor material protruding from the planar substrate and extending along a first direction: US7202517B2 · US6525403B2
the first fin of semiconductor material comprises a highly doped region located along one or more outer edges of the first fin of semiconductor material: US6525403B2
a gate region protruding from the planar substrate as a second fin that overlies the first fin of semiconductor material: US7202517B2 · US6525403B2
the gate region extends along a second direction perpendicular to the first direction: US7202517B2 · US6525403B2
a gate dielectric layer disposed between the highly doped region and the gate region: US7202517B2 · US6525403B2
the highly doped region extends from a top of the first fin of semiconducting material to a location that is substantially aligned with a bottom surface of the gate region: not shown

Element coverage — claim 15

A Fin field effect transistor (FinFET) device: US7202517B2 · US6525403B2
a first fin of semiconducting material protruding from a top surface of a semiconductor substrate and extending along a first direction: US7202517B2 · US6525403B2
a gate region protruding from the top surface of the semiconductor substrate as a second fin that extends along a second direction perpendicular to the first direction and which overlies the first fin: US7202517B2 · US6525403B2
a region located along a top surface and sidewalls of the first fin of semiconducting material: US7202517B2 · US6525403B2
the region having a first doping concentration that is higher than a second doping concentration of underlying sections of the first fin of semiconducting material: US6525403B2
the region is laterally disposed between source and drain regions that vertically extend to positions that are below the gate region: US7202517B2 · US6525403B2
a gate dielectric layer disposed between the gate region and a top surface and sidewalls of the region: US7202517B2 · US6525403B2

⚠ Key weakness US7202517B2 is a textbook teaching-away reference: its entire stated purpose is that the surface region be LOWLY doped to reduce ionized-impurity scattering and preserve carrier mobility ('high surface mobility of the carriers is obtained because ionized impurity scattering is reduced'). Reversing that to a highly-doped surface would defeat the reference's intended purpose and change its principle of operation (MPEP §§ 2143.01, 2145).

Anticipated counterarguments

1.US7202517B2 expressly criticizes/discourages high surface doping ('when inversion occurs near the surface of the fin, the carrier mobility is degraded due to ionized impurity scattering ... lower saturation current, which slows down the device'), a direct teaching away that negates any motivation to substitute higher surface doping (MPEP § 2141.02).
2.The proposed substitution would render US7202517B2 unsatisfactory for its intended purpose (mobility enhancement via low surface doping), so the modification is improper.
3.The claimed region is 'non-conductive'/highly resistive to increase effective oxide thickness — an inverse functional role from US7202517B2's mobility-preserving low-doped surface, so the references do not point toward the claimed structure.

Chart: US6525403B2 — Semiconductor device having MIS field effect transistors or three-dimensional structure vs. claim 1 →Chart: US6525403B2 — Semiconductor device having MIS field effect transistors or three-dimensional structure vs. claim 9 →Chart: US6525403B2 — Semiconductor device having MIS field effect transistors or three-dimensional structure vs. claim 15 →Chart: US7202517B2 — Multiple gate semiconductor device and method for forming same vs. claim 1 →Chart: US7202517B2 — Multiple gate semiconductor device and method for forming same vs. claim 9 →Chart: US7202517B2 — Multiple gate semiconductor device and method for forming same vs. claim 15 →

§103 · ObviousnessWEAKMPEP §2143(C)

US20110272763A1US20110272763A1US6525403B2US6525403B2US7348284B2US7348284B2

Independent claims charted: 9, 15 · dependent coverage asserted, not charted: 16, 18

US20110272763A1 is reasonably pertinent art (same fin-transistor field; addresses current non-uniformity) that teaches a deliberately higher-resistance, higher/differently-doped region in the top of the fin, supporting the 'region having a first doping concentration higher than underlying sections' (claim 15) and the 'non-conductive highly doped region' concept (claim 8/16). Combined with US7348284B2's wrapping geometry and US6525403B2's higher-doped surface, the combination would arrive at a resistive higher-doped edge region between the fin and gate dielectric, of the same semiconductor material as the fin (claim 18).

Motivation to combine

US20110272763A1 addresses a problem closely related to the target (non-uniform current distribution in fin channels, an effect connected to carrier/hot-carrier behavior) by forming a high-resistivity/higher-net-doped region in the upper portion of the fin ('a resistance region formed in an upper portion of the fin-shaped semiconductor region adjacent to the gate electrode, the resistance region having a resistivity higher than that of the extension regions'; 'the resistance region is doped with an impurity of a conductivity type opposite to a conductivity type of the extension region'). A PHOSITA concerned with the same current-uniformity/hot-carrier problem could apply that known high-resistivity-region technique, together with US7348284B2's conformal top-and-sidewall wrapping geometry and US6525403B2's higher-doped surface concept, to place a resistive higher-doped region along the fin edges under the gate.

⚠ Key weakness US20110272763A1 expressly forms its resistance region OUTSIDE the gate, in the extension/upper portion 'except a portion of the fin-shaped semiconductor region located beneath the gate electrode' — the opposite location from the target's requirement that the region sit under the gate between the channel and gate dielectric. Its region is also confined to the upper (top) portion, not wrapping the sidewalls.

Anticipated counterarguments

1.US20110272763A1's resistance region is deliberately placed in the extension outside the gate and only in the fin's upper portion; the target requires the highly-doped region under the gate along multiple edges of the channel — the references do not disclose or suggest that location or geometry (missing element under MPEP § 2131 and no rational underpinning to relocate it).
2.US20110272763A1 achieves high resistivity via amorphization or opposite-conductivity-type counter-doping, a different mechanism than the target's highly-doped same-type region increasing effective oxide thickness, so a PHOSITA would not predictably reach the claimed structure.
3.The three-reference combination requires selecting and relocating disparate teachings (extension resistance region + channel wrapping layer + top-surface high doping), which invites a hindsight-reconstruction challenge.

Unverified leads (no established date — not usable as grounds)

These references had no establishable date, so they were withheld from the grounds analysis — an undated reference cannot anchor a §102/§103 ground. Undated web results are often post-priority commentary describing the target’s own commercialized feature; treat these strictly as leads to date manually.

NPLCompact modelling and parameter extraction of nanoscale FinFETs
NPLDevice Modeling and Performance Analysis of FinFETs for Advanced Technology Nodes Using TCAD
NPLBottom Oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node
NPLOptimization of Pie-gate Bulk FinFET Structure
NPLEnhanced Circuit Densities in Epitaxially Defined FinFETs (EDFinFETs) over FinFETs
NPLSelf-Heating Effect Coupled Compact Model to Predict Hot Carrier Injection Degradation in Nanoscale Bulk FinFETs Under Different Conditions
NPLDevelopment and Analysis of a Three-Fin Trigate Q-FinFET for a 3 nm Technology Node with a Strained-Silicon Channel System
NPLThe Impact of Hysteresis Effect on Device Characteristic and Reliability for Various Fin-Widths Tri-Gate Hf0.5Zr0.5O2 Ferroelectric FinFET

Claim Charts

Element-by-element mapping of the strongest prior-art references against the target’s independent claims, constructed from the retrieved claim text. A single — (not disclosed) element defeats §102 anticipation for that reference; it may still contribute to a §103 combination. Confirm every quotation against the reference itself.

Chart index — references × independent claims

Reference	Cl. 1	Cl. 9	Cl. 15
US6525403B2 — Semiconductor device having MIS field effect transistors or three-dimensional structure	—	—	—
US7015078B1 — Silicon on insulator substrate having improved thermal conductivity and method of its formation	—	—	—
US7202517B2 — Multiple gate semiconductor device and method for forming same	—	—	—
US7262086B2 — Contacts to semiconductor fin devices	—	·	·

ELEMENT(S) NOT SHOWN6 / 7 elements

The reference maps cleanly onto the structural backbone of claim 1: a semiconductor projection (fin) protruding from a substrate with a bottom connected to the substrate (element 2), a channel defined by a gate electrode over the fin side surfaces with source/drain on either side (element 3), and a gate electrode over the side/top surfaces with an interposed gate insulating film (elements 5-6, partially, subject to the 'second fin'/'protruding' framing). The critical gap is the 'highly doped region located along MULTIPLE outer edges of the channel region' (element 4) and the requirement that this region be 'vertically AND laterally arranged between the channel region and the gate dielectric layer' (element 7). The reference's closest teaching (dependent claims 2 and 5) is a higher-doped 'third impurity region' formed ONLY in the top surface of the projection — a single edge, not multiple outer edges — and it is described as a top-surface region, not one wrapping the sidewalls in the vertical-and-lateral configuration the claim requires. On the provided text, element 4 is only partially disclosed and element 7 is absent, so this single reference would NOT anticipate claim 1 under §102; the patentee's strongest counterargument is that the reference's highly-doped region is confined to the top surface and does not run along the fin sidewalls/multiple edges as claimed. The reference could nonetheless contribute to a §103 combination (e.g., with a sidewall-wrapping doped-region teaching), which is outside the scope of this anticipation chart. This is candidate prior-art analysis for attorney review, not a legal opinion or validity determination.

US6525403B2 — Semiconductor device having MIS field effect transistors or three-dimensional structure vs. claim 1

Status glyph	Claim element	Status	Disclosure / notes	Location
◐	A Fin field effect transistor (FinFET) device	Partially disclosed	“A semiconductor projection is formed on a semiconductor substrate of the first conductivity type and has a semiconductor layer of the first conductivity type. The semiconductor projection has a top surface and side surfaces. A gate electrode is formed above at least the side surfaces of the semiconductor projection.”	claim 1 / Abstract
✓	a first fin of semiconducting material protruding from a semiconductor substrate	Disclosed	“a semiconductor projection of the first conductivity type comprising a first side surface and a second side surface formed between the first portion and the second portion of the insulating film, the semiconductor projection being projected from a surface of the insulating film, a bottom of the semiconductor projection being connected to the semiconductor substrate”	claim 1
✓	the first fin of semiconducting material comprises a channel region	Disclosed	“a gate electrode formed on the first side surface of the semiconductor projection with a gate insulating film interposed therebetween; a source region and a drain region of a second conductivity type formed in the first side surface of the semiconductor projection, the source region and the drain region being located on both sides of the gate electrode”	claim 1
◐	the first fin of semiconducting material comprises a highly doped region located along multiple outer edges of the channel region	Partially disclosed	“further comprising a third impurity region of the first conductivity type formed in the top surface of the semiconductor projection, the third impurity region being higher in doping level than the semiconductor layer of the semiconductor projection”	claim 2 / claim 5
◐	a gate region protruding from the semiconductor substrate as a second fin that overlies the first fin of semiconducting material	Partially disclosed	“a gate electrode formed on the side surfaces and the top surface of the semiconductor projection with a gate insulating film interposed therebetween, the gate electrode comprising a top surface parallel to a surface of the semiconductor substrate”	claim 16 / claim 7
◐	a gate dielectric layer located between the highly doped region and the gate region	Partially disclosed	“a gate electrode formed on the side surfaces and the top surface of the semiconductor projection with a gate insulating film interposed therebetween”	claim 7 / claim 16
—	the highly doped region is vertically and laterally arranged between the channel region and the gate dielectric layer	Not disclosed	—	—

ELEMENT(S) NOT SHOWN7 / 8 elements

For attorney review — not a legal opinion, not a validity determination. Against claim 9, US6525403B2 maps cleanly on the general three-dimensional MISFET architecture: it discloses a semiconductor substrate (element 2), a semiconductor projection protruding from the substrate that carries the channel (element 3), a gate electrode over the projection's side/top surfaces (elements 5-7, partial), and a gate crossing perpendicular to the source-drain direction (element 6, partial). Its dependent claim 2 discloses a higher-doped 'third impurity region ... formed in the top surface of the semiconductor projection,' which arguably reads on element 4's 'highly doped region located along one or more outer edges' since the top surface is one outer edge — but this is only partial, because the reference's highly-doped region is confined to the TOP surface and is not described as running along the sidewalls. The dispositive gap is element 8: the reference nowhere discloses a highly doped region that 'extends from a top of the first fin ... to a location that is substantially aligned with a bottom surface of the gate region.' The third impurity region is expressly a top-surface region only, so this limitation is absent, and the gate-dielectric-between-highly-doped-region-and-gate limitation (element 7) is correspondingly weak because the disclosed gate insulating film sits between the sidewall and gate rather than between the top-surface doped region and gate. Note also that all of the reference disclosures relied on are drawn from its CLAIMS text only; the specification/figures were not provided, so several mappings (e.g., the 'second fin' gate and perpendicular orientation) are UNVERIFIED beyond the claim language quoted. Because at least element 8 is absent, this single reference would NOT anticipate claim 9 under §102 (MPEP § 2131); the patentee's best counterargument is that the highly-doped 'third impurity region' is limited to the top surface and lacks the top-to-gate-bottom vertical extent the claim requires. The reference may still be relevant to a §103 combination, which is outside this single-reference anticipation chart.

⚠ Unverified reference quotation in claim chart (US6525403B2 — Semiconductor device having MIS field effect transistors or three-dimensional structure vs. claim 9): "a semiconductor projection of the first conductivity type comprising a first side surface and a second side surface f…" does not appear verbatim in the fetched reference text. Correct the quote or treat the disclosure as unverified before relying on it.
⚠ Unverified reference quotation in claim chart (US6525403B2 — Semiconductor device having MIS field effect transistors or three-dimensional structure vs. claim 9): "a semiconductor projection of the first conductivity type comprising a first side surface and a second side surface .…" does not appear verbatim in the fetched reference text. Correct the quote or treat the disclosure as unverified before relying on it.

US6525403B2 — Semiconductor device having MIS field effect transistors or three-dimensional structure vs. claim 9

Status glyph	Claim element	Status	Disclosure / notes	Location
◐	A Fin field effect transistor (FinFET) device	Partially disclosed	“a semiconductor projection of the first conductivity type comprising a first side surface and a second side surface formed between the first portion and the second portion of the insulating film, the semiconductor projection being projected from a surface of the insulating film ... a gate electrode formed on the side surfaces and the top surface of the semiconductor projection with a gate insulating film interposed therebetween”	Claim 1; Claim 16 (title/abstract)
✓	a planar substrate comprising a semiconductor material	Disclosed	“a semiconductor substrate of a first conductivity type”	Claim 1
✓	a channel region comprising a first fin of semiconductor material protruding from the planar substrate and extending along a first direction	Disclosed	“a semiconductor projection of the first conductivity type comprising a first side surface and a second side surface ... the semiconductor projection being projected from a surface of the insulating film, a bottom of the semiconductor projection being connected to the semiconductor substrate”	Claim 1
◐	the first fin of semiconductor material comprises a highly doped region located along one or more outer edges of the first fin of semiconductor material	Partially disclosed	“a third impurity region of the first conductivity type formed in the top surface of the semiconductor projection, the third impurity region being higher in doping level than the semiconductor layer of the semiconductor projection”	Claim 2
◐	a gate region protruding from the planar substrate as a second fin that overlies the first fin of semiconductor material	Partially disclosed	“a gate electrode formed on the gate insulating film on the first side surface of the semiconductor projection and above the top surface of the semiconductor projection”	Claim 7; Claim 16
◐	the gate region extends along a second direction perpendicular to the first direction	Partially disclosed	“the length in the direction parallel to the surface of the semiconductor substrate and perpendicular to the direction from the source region to the drain region of the portion of the semiconductor projection on which the gate electrode is located”	Claim 3
◐	a gate dielectric layer disposed between the highly doped region and the gate region	Partially disclosed	“a gate electrode formed on the first side surface of the semiconductor projection with a gate insulating film interposed therebetween”	Claim 1; Claim 7
—	the highly doped region extends from a top of the first fin of semiconducting material to a location that is substantially aligned with a bottom surface of the gate region	Not disclosed	—	—

ELEMENT(S) NOT SHOWN7 / 7 elements

The reference discloses a three-dimensional MIS FET (a fin-type transistor): a semiconductor projection protruding from an insulating-film surface with its bottom connected to the substrate (element 2 maps cleanly), a gate electrode over the side surfaces and top surface with a gate insulating film interposed (elements 1, 3, and 7 map in part), and source/drain regions on both sides of the gate (element 6 in part). The critical gap is the claimed 'region located along a top surface AND sidewalls' of the fin having a higher doping concentration than the underlying fin. The reference's higher-doped 'third impurity region' is expressly formed ONLY 'in the top surface of the semiconductor projection' (claims 2, 5) — the available text does not disclose that higher-doped region extending along the sidewalls of the fin, as claim 15 requires. Because element 4 (and correspondingly the sidewall aspects of elements 5 and 7) is not disclosed as arranged in the claim, a single-reference §102 anticipation is not made out on the text provided. Note also that only the abstract and claims of US6525403B2 were provided; the detailed description and figures were not available, so all mappings above are UNVERIFIED against the full specification and should be confirmed before reliance. This reference may nonetheless be relevant to a §103 combination (e.g., with references teaching sidewall doping) for the attorney to evaluate.

US6525403B2 — Semiconductor device having MIS field effect transistors or three-dimensional structure vs. claim 15

Status glyph	Claim element	Status	Disclosure / notes	Location
◐	A Fin field effect transistor (FinFET) device	Partially disclosed	“A semiconductor projection is formed on a semiconductor substrate of the first conductivity type and has a semiconductor layer of the first conductivity type. The semiconductor projection has a top surface and side surfaces. A gate electrode is formed above at least the side surfaces of the semiconductor projection.”	Abstract; claim 16
✓	a first fin of semiconducting material protruding from a top surface of a semiconductor substrate and extending along a first direction	Disclosed	“a semiconductor projection of the first conductivity type comprising a first side surface and a second side surface formed between the first portion and the second portion of the insulating film, the semiconductor projection being projected from a surface of the insulating film, a bottom of the semiconductor projection being connected to the semiconductor substrate”	claim 1
◐	a gate region protruding from the top surface of the semiconductor substrate as a second fin that extends along a second direction perpendicular to the first direction and which overlies the first fin	Partially disclosed	“a gate electrode formed on the side surfaces and the top surface of the semiconductor projection with a gate insulating film interposed therebetween, the gate electrode comprising a top surface parallel to a surface of the semiconductor substrate”	claim 16
◐	a region located along a top surface and sidewalls of the first fin of semiconducting material	Partially disclosed	“a third impurity region of the first conductivity type formed in the top surface of the semiconductor projection, the third impurity region being higher in doping level than the semiconductor layer of the semiconductor projection”	claim 2; claim 5
◐	the region having a first doping concentration that is higher than a second doping concentration of underlying sections of the first fin of semiconducting material	Partially disclosed	“the third impurity region being higher in doping level than the semiconductor layer of the semiconductor projection”	claim 2
◐	the region is laterally disposed between source and drain regions that vertically extend to positions that are below the gate region	Partially disclosed	“a source region and a drain region of a second conductivity type formed in the first side surface of the semiconductor projection, the source region and the drain region being located on both sides of the gate electrode”	claim 1
◐	a gate dielectric layer disposed between the gate region and a top surface and sidewalls of the region	Partially disclosed	“a gate electrode formed on the side surfaces and the top surface of the semiconductor projection with a gate insulating film interposed therebetween”	claim 16

ELEMENT(S) NOT SHOWN5 / 7 elements

This reference is directed to an SOI substrate with a silicon carbide thermal-dissipation layer, and only incidentally discloses that a FinFET may be formed on that substrate. The generic FinFET elements map cleanly: the reference expressly recites a 'FinFET body ... comprising source and drain regions joined by a channel region' (element 1, 3), patterned from a semiconductor layer on an SOI substrate (element 2, partially — the reference does not describe a fin 'protruding' or its geometry), and a 'gate insulator' with a 'gate around the channel region' (elements 5 and 6, partially — no 'second fin' geometry and no 'highly doped region' as the reference structure). Critically, the reference contains NO disclosure of the claim's central limitation — a 'highly doped region located along multiple outer edges of the channel region' (element 4) that is 'vertically and laterally arranged between the channel region and the gate dielectric layer' (element 7). Because at least these two dispositive limitations are entirely absent from the single reference, US7015078B1 would NOT anticipate claim 1 under §102/MPEP § 2131; the verdict is missing_elements. (This is a candidate prior-art analysis for attorney review — not a legal opinion or validity determination.)

⚠ Unverified reference quotation in claim chart (US7015078B1 — Silicon on insulator substrate having improved thermal conductivity and method of its formation vs. claim 1): "providing an SOI substrate comprising a silicon carbide thermal dissipation layer, a dielectric layer formed on the s…" does not appear verbatim in the fetched reference text. Correct the quote or treat the disclosure as unverified before relying on it.

US7015078B1 — Silicon on insulator substrate having improved thermal conductivity and method of its formation vs. claim 1

Status glyph	Claim element	Status	Disclosure / notes	Location
✓	A Fin field effect transistor (FinFET) device	Disclosed	“patterning a FinFET body from the semiconductor material, the FinFET body comprising source and drain regions joined by a channel region”	claim 6
◐	a first fin of semiconducting material protruding from a semiconductor substrate	Partially disclosed	“providing an SOI substrate comprising a silicon carbide thermal dissipation layer, a dielectric layer formed on the silicon carbide layer, and a layer of a semiconductor material formed on the dielectric layer; ... patterning a FinFET body from the semiconductor material”	claim 6
✓	the first fin of semiconducting material comprises a channel region	Disclosed	“the FinFET body comprising source and drain regions joined by a channel region”	claim 6
—	the first fin of semiconducting material comprises a highly doped region located along multiple outer edges of the channel region	Not disclosed	—	—
◐	a gate region protruding from the semiconductor substrate as a second fin that overlies the first fin of semiconducting material	Partially disclosed	“forming a gate around the channel region, the gate being separated from the channel region by the gate insulator”	claim 6
◐	a gate dielectric layer located between the highly doped region and the gate region	Partially disclosed	“forming a gate insulator around at least the channel region; and forming a gate around the channel region, the gate being separated from the channel region by the gate insulator”	claim 6
—	the highly doped region is vertically and laterally arranged between the channel region and the gate dielectric layer	Not disclosed	—	—

ELEMENT(S) NOT SHOWN5 / 8 elements

US7015078B1 is directed to an SOI substrate with a silicon carbide thermal-dissipation layer and methods of fabricating SOI devices; among its claims it recites 'patterning a FinFET body ... comprising source and drain regions joined by a channel region' and 'forming a gate insulator' and a gate around the channel region, which map (at least partially) to the generic FinFET, channel-fin, gate, and gate-dielectric limitations of claim 9. However, the reference contains no disclosure whatsoever of the central inventive limitations: a 'highly doped region located along one or more outer edges of the first fin' (element 4) and that region 'extend[ing] from a top of the first fin ... to a location that is substantially aligned with a bottom surface of the gate region' (element 8). The reference also does not expressly disclose the gate as a second fin extending perpendicular to the fin (element 6). Because at least these limitations are entirely absent from this single reference, it would NOT anticipate claim 9 under §102 (MPEP § 2131); the FinFET-body teaching could at most be offered as a component of a §103 combination for the attorney to evaluate. Note also this reference's claims are method claims, whereas claim 9 is an apparatus claim — an additional mapping caveat. For attorney review — not a legal opinion, not a validity determination.

US7015078B1 — Silicon on insulator substrate having improved thermal conductivity and method of its formation vs. claim 9

Status glyph	Claim element	Status	Disclosure / notes	Location
✓	A Fin field effect transistor (FinFET) device	Disclosed	“patterning a FinFET body from the semiconductor material, the FinFET body comprising source and drain regions joined by a channel region”	claim 6
◐	a planar substrate comprising a semiconductor material	Partially disclosed	“providing an SOI substrate comprising a silicon carbide thermal dissipation layer, a dielectric layer formed on the silicon carbide layer, and a layer of a semiconductor material formed on the dielectric layer”	claim 6 / claim 11
◐	a channel region comprising a first fin of semiconductor material protruding from the planar substrate and extending along a first direction	Partially disclosed	“patterning a FinFET body from the semiconductor material, the FinFET body comprising source and drain regions joined by a channel region”	claim 6
—	the first fin of semiconductor material comprises a highly doped region located along one or more outer edges of the first fin of semiconductor material	Not disclosed	—	—
◐	a gate region protruding from the planar substrate as a second fin that overlies the first fin of semiconductor material	Partially disclosed	“forming a gate around the channel region, the gate being separated from the channel region by the gate insulator”	claim 6
—	the gate region extends along a second direction perpendicular to the first direction	Not disclosed	—	—
◐	a gate dielectric layer disposed between the highly doped region and the gate region	Partially disclosed	“forming a gate insulator around at least the channel region”	claim 6
—	the highly doped region extends from a top of the first fin of semiconducting material to a location that is substantially aligned with a bottom surface of the gate region	Not disclosed	—	—

ELEMENT(S) NOT SHOWN5 / 7 elements

The available text of US7015078B1 (a thermal-conductivity SOI substrate patent) discloses a generic FinFET body with source and drain regions joined by a channel region (element 1, and portions of elements 2, 3, 6 and 7 relating to the fin, gate and gate insulator). However, the reference is directed to a silicon-carbide thermal-dissipation SOI substrate and its process; the fetched text says nothing about a doped 'region' along the top surface and sidewalls of the fin having a doping concentration higher than the underlying fin sections. Elements 4 and 5 — the core inventive limitation of claim 15 (the higher-doped region along the top/sidewalls of the fin) — are entirely ABSENT, and elements 2, 3, 6 and 7 are only partially met because the provided text does not expressly describe fin protrusion directions, a perpendicular gate 'second fin', or the source/drain/gate geometry with the specificity claimed. Because at least one limitation (the higher-doped region) is missing from this single reference, it would NOT anticipate claim 15 under §102 (MPEP § 2131); no §102 cure is available by combining references. This is candidate prior-art analysis for attorney review, not a legal opinion or validity determination.

US7015078B1 — Silicon on insulator substrate having improved thermal conductivity and method of its formation vs. claim 15

Status glyph	Claim element	Status	Disclosure / notes	Location
✓	A Fin field effect transistor (FinFET) device	Disclosed	“patterning a FinFET body from the semiconductor material, the FinFET body comprising source and drain regions joined by a channel region”	claim 6
◐	a first fin of semiconducting material protruding from a top surface of a semiconductor substrate and extending along a first direction	Partially disclosed	“patterning a FinFET body from the semiconductor material, the FinFET body comprising source and drain regions joined by a channel region”	claim 6
◐	a gate region protruding from the top surface of the semiconductor substrate as a second fin that extends along a second direction perpendicular to the first direction and which overlies the first fin	Partially disclosed	“forming a gate around the channel region, the gate being separated from the channel region by the gate insulator”	claim 6
—	a region located along a top surface and sidewalls of the first fin of semiconducting material	Not disclosed	—	—
—	the region having a first doping concentration that is higher than a second doping concentration of underlying sections of the first fin of semiconducting material	Not disclosed	—	—
◐	the region is laterally disposed between source and drain regions that vertically extend to positions that are below the gate region	Partially disclosed	“the FinFET body comprising source and drain regions joined by a channel region”	claim 6
◐	a gate dielectric layer disposed between the gate region and a top surface and sidewalls of the region	Partially disclosed	“forming a gate insulator around at least the channel region”	claim 6

ELEMENT(S) NOT SHOWN5 / 7 elements

US7202517B2 cleanly maps the generic FinFET architecture of claim 1: a FinFET device (claim 2), a fin of semiconducting material carrying source/drain and a channel region, a gate straddling multiple sides of the fin, and an interposed gate dielectric (107b). However, the reference is directed to a RETROGRADE doping profile that is the structural INVERSE of the key claim limitation. Claim 1 requires a HIGHLY DOPED region located along the multiple outer edges of the channel, vertically and laterally arranged between the channel and the gate dielectric. The reference expressly teaches that the region between the gate structure and the sidewalls of the bulk is LOWLY doped: claim 1 of the reference states 'the surface region is located between the gate structure and two sidewalls of the bulk region, wherein the bulk region has a first dopant concentration level and the surface region has a second dopant concentration level, and wherein the second dopant concentration level is less than the first dopant concentration level,' and the specification describes 'lowly doped regions 106 a ... formed at or near the interface between the fin 106 and the gate dielectric 107 b along each of the sidewalls of the fin 106.' The highly doped material in the reference is the BULK/interior of the fin, not the outer edges. Elements (4) and (7) — the highly doped region located along the outer edges and interposed between channel and gate dielectric — are therefore ABSENT, and elements (6)-(7) are only partially met because the interposed layer is the lowly doped surface region, not a highly doped region. Because at least one limitation is missing and the reference teaches away by placing low (not high) doping at the surface, this reference would NOT anticipate claim 1 under §102; the missing 'highly doped outer edge' limitation is dispositive of anticipation, though the reference remains relevant background for any §103 analysis (subject to a motivation-to-combine showing). This is candidate prior-art analysis for attorney review, not a legal opinion or validity determination.

US7202517B2 — Multiple gate semiconductor device and method for forming same vs. claim 1

Status glyph	Claim element	Status	Disclosure / notes	Location
✓	A Fin field effect transistor (FinFET) device	Disclosed	“The device of claim 1 , wherein the multi-gate semiconductor device is a FinFET device and the semiconductor body comprises a fin of the FinFET device.”	Claim 2; Detailed Description (FIG. 2 device 200)
✓	a first fin of semiconducting material protruding from a semiconductor substrate	Disclosed	“The FinFET device 100 includes a source region 104 and a drain 105 region connected by a fin 106 , where the fin 106 is located in between the source region 104 and the drain region 105 . As may be seen in FIG. 1 , the source region 104 , the drain region 105 and the fin 106 are formed from the semiconductor layer 102 .”	Detailed Description, §1 (FIG. 1a)
✓	the first fin of semiconducting material comprises a channel region	Disclosed	“The channel of the FinFET 100 will be the portion of the fin 106 that is covered by and, depending on the thickness of the gate dielectric, that is under electrical control of the gate voltages applied to the gate 107”	Detailed Description, §1
—	the first fin of semiconducting material comprises a highly doped region located along multiple outer edges of the channel region	Not disclosed	—	—
◐	a gate region protruding from the semiconductor substrate as a second fin that overlies the first fin of semiconducting material	Partially disclosed	“The gate 107 overlies the fin 106 on three of its sides (e.g., the top surface and two sidewall surfaces).”	Detailed Description, §1 (FIG. 1a/1b); Claim 1
◐	a gate dielectric layer located between the highly doped region and the gate region	Partially disclosed	“the gate 107 includes a gate dielectric 107 b and a gate electrode layer 107 a”	Detailed Description, §1 (FIG. 1b)
—	the highly doped region is vertically and laterally arranged between the channel region and the gate dielectric layer	Not disclosed	—	—

ELEMENT(S) NOT SHOWN6 / 8 elements

The reference maps cleanly onto the generic FinFET architecture of claim 9 — a semiconductor substrate, a channel fin protruding and extending along a first direction, a gate straddling the fin perpendicular to it, and a gate dielectric between the fin surface and the gate. However, the claim's dispositive limitation — a HIGHLY doped region located along the outer edges of the fin, positioned between the channel and gate dielectric (elements 4, 7, and 8) — is ABSENT and, indeed, the reference teaches the OPPOSITE arrangement. US7202517B2 discloses a 'retrograde' profile in which the surface/edge region is LOWLY doped and the interior bulk is highly doped ('the surface region is located between the gate structure and two sidewalls of the bulk region, wherein the bulk region has a first dopant concentration level and the surface region has a second dopant concentration level, and wherein the second dopant concentration level is less than the first dopant concentration level,' claim 1; 'FIG. 6 a illustrates a patterned fin with a highly doped body, FIG. 6 b illustrates the formation of a lowly doped surface layer enveloping the highly doped body'). Because the reference places the highly doped material in the bulk and the lowly doped material along the edges/interface — the inverse of what claim 9 requires — element 4 and its dependent structural limitations (7, 8) are not disclosed. Under §102/MPEP § 2131, the absence of even one claimed limitation (here, three interrelated limitations, taught oppositely) defeats anticipation. Verdict: missing_elements. This candidate reference may nonetheless be relevant to a §103 analysis, but the patentee's strongest counterargument — that the reference teaches away by disclosing a lowly-doped rather than highly-doped edge region — should be weighed by the attorney.

⚠ Unverified reference quotation in claim chart (US7202517B2 — Multiple gate semiconductor device and method for forming same vs. claim 9): "The FinFET device 100 includes a semiconductor layer 102 disposed on a substrate 101 ... The substrate 101 may be a s…" does not appear verbatim in the fetched reference text. Correct the quote or treat the disclosure as unverified before relying on it.
⚠ Unverified reference quotation in claim chart (US7202517B2 — Multiple gate semiconductor device and method for forming same vs. claim 9): "The FinFET device 100 includes a source region 104 and a drain 105 region connected by a fin 106 , where the fin 106 …" does not appear verbatim in the fetched reference text. Correct the quote or treat the disclosure as unverified before relying on it.

US7202517B2 — Multiple gate semiconductor device and method for forming same vs. claim 9

Status glyph	Claim element	Status	Disclosure / notes	Location
✓	A Fin field effect transistor (FinFET) device	Disclosed	“The device of claim 1 , wherein the multi-gate semiconductor device is a FinFET device and the semiconductor body comprises a fin of the FinFET device.”	Claim 2; Detailed Description (FIG. 1a)
✓	a planar substrate comprising a semiconductor material	Disclosed	“The FinFET device 100 includes a semiconductor layer 102 disposed on a substrate 101 ... The substrate 101 may be a semiconductor substrate, e.g. silicon.”	Detailed Description, FIG. 1a (substrate 101)
✓	a channel region comprising a first fin of semiconductor material protruding from the planar substrate and extending along a first direction	Disclosed	“The FinFET device 100 includes a source region 104 and a drain 105 region connected by a fin 106 , where the fin 106 is located in between the source region 104 and the drain region 105 ... a thin gate line straddles a thin silicon channel fin.”	Detailed Description, FIG. 1a (fin 106); Background
—	the first fin of semiconductor material comprises a highly doped region located along one or more outer edges of the first fin of semiconductor material	Not disclosed	—	Claim 1; Summary; FIG. 2/FIG. 6 (retrograde profile)
◐	a gate region protruding from the planar substrate as a second fin that overlies the first fin of semiconductor material	Partially disclosed	“A gate 107 , which includes a gate dielectric layer and a gate electrode layer (not separately designated), is also shown in FIG. 1 a . The gate 107 overlies the fin 106 on three of its sides (e.g., the top surface and two sidewall surfaces).”	Detailed Description, FIG. 1a/1b (gate 107); Claim 1
✓	the gate region extends along a second direction perpendicular to the first direction	Disclosed	“In such FinFETs, a thin gate line straddles a thin silicon channel fin.”	Background (Hisamoto FinFET description)
◐	a gate dielectric layer disposed between the highly doped region and the gate region	Partially disclosed	“lowly doped regions 106 a are formed at or near the interface between the fin 106 and the gate dielectric 107 b along each of the sidewalls of the fin 106 .”	Detailed Description, FIG. 2b (gate dielectric 107b, regions 106a)
—	the highly doped region extends from a top of the first fin of semiconducting material to a location that is substantially aligned with a bottom surface of the gate region	Not disclosed	—	N/A

ELEMENT(S) NOT SHOWN6 / 7 elements

For attorney review — not a legal opinion, not a validity determination. US7202517B2 maps cleanly onto the FinFET structural framing of claim 15 (FinFET device, fin between source/drain on a substrate, gate straddling/overlying the fin on three sides, gate dielectric between gate and fin, and a distinct surface region running along the top and sidewalls of the fin). However, the dispositive limitation — element (5), a surface region whose doping concentration is HIGHER than the underlying sections of the fin — is ABSENT. The reference expressly teaches the inverse (a 'retrograde' profile): its surface region 106a is a LOWLY doped region and the bulk 106b is more highly doped ('the surface region has a second dopant concentration level, and wherein the second dopant concentration level is less than the first dopant concentration level'; 'lowly doped region 106 a ... along the top surface of the fin'). Because a single reference must disclose every limitation arranged as in the claim (§102 / MPEP § 2131), and this reference discloses the opposite doping relationship (arguably teaching away), it would NOT anticipate claim 15; at most it is a candidate §103 building block, but the higher-doped-surface limitation would still need to be supplied by other art with an articulated motivation. Elements (3) and (6) are additionally only partially spelled out (perpendicular 'second fin' gate geometry and the source/drain vertical-extent language are not verbatim in the provided text).

US7202517B2 — Multiple gate semiconductor device and method for forming same vs. claim 15

Status glyph	Claim element	Status	Disclosure / notes	Location
✓	A Fin field effect transistor (FinFET) device	Disclosed	“The device of claim 1 , wherein the multi-gate semiconductor device is a FinFET device and the semiconductor body comprises a fin of the FinFET device.”	Claim 2; Description ¶ 'One non-classical CMOS device'
✓	a first fin of semiconducting material protruding from a top surface of a semiconductor substrate and extending along a first direction	Disclosed	“The FinFET device 100 includes a source region 104 and a drain 105 region connected by a fin 106 , where the fin 106 is located in between the source region 104 and the drain region 105 . As may be seen in FIG. 1 , the source region 104 , the drain region 105 and the fin 106 are formed from the semiconductor layer 102 .”	Description, FIG. 1a discussion
◐	a gate region protruding from the top surface of the semiconductor substrate as a second fin that extends along a second direction perpendicular to the first direction and which overlies the first fin	Partially disclosed	“The gate 107 overlies the fin 106 on three of its sides (e.g., the top surface and two sidewall surfaces).”	Description, FIG. 1a/1b discussion; Background
✓	a region located along a top surface and sidewalls of the first fin of semiconducting material	Disclosed	“For the FinFET 300 a lowly doped region 106 a is also formed along the top surface of the fin 106 in addition to the lowly doped regions 106 a formed along the sidewalls of the fin 106 ).”	Description, FIG. 3 (triple gate) discussion
—	the region having a first doping concentration that is higher than a second doping concentration of underlying sections of the first fin of semiconducting material	Not disclosed	—	N/A — reference teaches the opposite (retrograde) profile
◐	the region is laterally disposed between source and drain regions that vertically extend to positions that are below the gate region	Partially disclosed	“the fin 106 is located in between the source region 104 and the drain region 105”	Description, FIG. 1a discussion
✓	a gate dielectric layer disposed between the gate region and a top surface and sidewalls of the region	Disclosed	“the gate 107 includes a gate dielectric 107 b and a gate electrode layer 107 a”	Description, FIG. 1b discussion

ELEMENT(S) NOT SHOWN2 / 7 elements

The available text of US7262086B2 is directed to a METHOD for forming electrical CONTACTS to a semiconductor fin (etch-stop layer, passivation layer, contact hole, conductive fill) — not to the internal doping architecture of a FinFET channel. It maps at most to the generic 'fin' hardware substrate of the claim: it discloses a semiconductor fin with a top surface and two sidewall surfaces (claims 1, 35) and a multiple-gate/double-gate/triple-gate transistor fin (claims 16-18), which partially reads on elements 1-2. However, every distinctive limitation of target claim 1 is ABSENT from the provided text: there is no disclosure of a channel region (element 3), no highly doped region located along multiple outer edges of the channel (element 4), no gate region overlying the fin as a second fin (element 5), no gate dielectric layer positioned between a highly doped region and the gate (element 6), and no highly doped region vertically and laterally arranged between the channel and the gate dielectric (element 7). The reference's only 'heavily doped' teaching (claims 15, 32, 44) refers to the CONTACT FILL material, not a doped channel-edge region, so it cannot supply element 4. Because at least five limitations are missing from this single reference, it would NOT anticipate claim 1 under §102 (MPEP § 2131); at most it could serve as a generic 'fin device' teaching in a §103 combination, subject to a separate motivation-to-combine analysis. This is candidate prior-art analysis for attorney review, not a legal opinion or validity determination.

US7262086B2 — Contacts to semiconductor fin devices vs. claim 1

Status glyph	Claim element	Status	Disclosure / notes	Location
◐	A Fin field effect transistor (FinFET) device	Partially disclosed	“A method for forming a contact to a multiple-gate transistor fin comprising the steps of: providing a multiple-gate transistor comprising a fin”	claim 16
◐	a first fin of semiconducting material protruding from a semiconductor substrate	Partially disclosed	“providing a semiconductor fin having a top surface, two sidewall surfaces and at least one end surface”	claim 1 / claim 35
—	the first fin of semiconducting material comprises a channel region	Not disclosed	—	—
—	the first fin of semiconducting material comprises a highly doped region located along multiple outer edges of the channel region	Not disclosed	—	—
—	a gate region protruding from the semiconductor substrate as a second fin that overlies the first fin of semiconducting material	Not disclosed	—	—
—	a gate dielectric layer located between the highly doped region and the gate region	Not disclosed	—	—
—	the highly doped region is vertically and laterally arranged between the channel region and the gate dielectric layer	Not disclosed	—	—

Priority-Date Discipline

Note

Deterministic comparison of each reference’s date as retrieved against the target’s stated priority date (2013-06-28). AIA regime assumed. A patent reference may carry an earlier effective date under §102(a)(2) than the date compared here — a reference excluded on its publication date may still qualify; confirm before discarding. The target’s priority claim is taken as stated, not validated.

Qualified prior art (8)

Reference	Date relied on	Basis
US6525403B2	2003-02-25	dated 2003-02-25 (publication), before the target's priority date 2013-06-28 — qualifies as prior art
US7015078B1	2006-03-21	dated 2006-03-21 (publication), before the target's priority date 2013-06-28 — qualifies as prior art
US7202517B2	2005-03-10	dated 2005-03-10 (publication), before the target's priority date 2013-06-28 — qualifies as prior art
US7262086B2	2007-08-28	dated 2007-08-28 (publication), before the target's priority date 2013-06-28 — qualifies as prior art
US7288823B2	2006-06-22	dated 2006-06-22 (publication), before the target's priority date 2013-06-28 — qualifies as prior art
US7348284B2	2006-02-16	dated 2006-02-16 (publication), before the target's priority date 2013-06-28 — qualifies as prior art
US20130026575A1	2013-01-31	dated 2013-01-31 (publication), before the target's priority date 2013-06-28 — qualifies as prior art
US20110272763A1	2011-11-10	dated 2011-11-10 (publication), before the target's priority date 2013-06-28 — qualifies as prior art

Excluded on date (4)

Reference	Date relied on	Basis
US20230143986A1	2023-05-11	dated 2023-05-11 (publication), on or after the target's priority date 2013-06-28 — NOT prior art; excluded from grounds
US20210013314A1	2021-01-14	dated 2021-01-14 (publication), on or after the target's priority date 2013-06-28 — NOT prior art; excluded from grounds
US20200168736A1	2020-05-28	dated 2020-05-28 (publication), on or after the target's priority date 2013-06-28 — NOT prior art; excluded from grounds
US12183822B2	2022-10-06	dated 2022-10-06 (publication), on or after the target's priority date 2013-06-28 — NOT prior art; excluded from grounds

No established date — verify manually (8)

Reference	Date relied on	Basis
Compact modelling and parameter extraction of nanoscale FinFETs	—	no date could be established for this reference — confirm it predates the target's priority date before relying on it
Device Modeling and Performance Analysis of FinFETs for Advanced Technology Nodes Using TCAD	—	no date could be established for this reference — confirm it predates the target's priority date before relying on it
Bottom Oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node	—	no date could be established for this reference — confirm it predates the target's priority date before relying on it
Optimization of Pie-gate Bulk FinFET Structure	—	no date could be established for this reference — confirm it predates the target's priority date before relying on it
Enhanced Circuit Densities in Epitaxially Defined FinFETs (EDFinFETs) over FinFETs	—	no date could be established for this reference — confirm it predates the target's priority date before relying on it
Self-Heating Effect Coupled Compact Model to Predict Hot Carrier Injection Degradation in Nanoscale Bulk FinFETs Under Different Conditions	—	no date could be established for this reference — confirm it predates the target's priority date before relying on it
Development and Analysis of a Three-Fin Trigate Q-FinFET for a 3 nm Technology Node with a Strained-Silicon Channel System	—	no date could be established for this reference — confirm it predates the target's priority date before relying on it
The Impact of Hysteresis Effect on Device Characteristic and Reliability for Various Fin-Widths Tri-Gate Hf0.5Zr0.5O2 Ferroelectric FinFET	—	no date could be established for this reference — confirm it predates the target's priority date before relying on it

Consistency checks

Automated checks run over the grounds before assembly — heuristics for attorney review, not legal conclusions.

⚠ Unverified reference quotation in claim chart (US6525403B2 — Semiconductor device having MIS field effect transistors or three-dimensional structure vs. claim 9): "a semiconductor projection of the first conductivity type comprising a first side surface and a second side surface f…" does not appear verbatim in the fetched reference text. Correct the quote or treat the disclosure as unverified before relying on it.
⚠ Unverified reference quotation in claim chart (US6525403B2 — Semiconductor device having MIS field effect transistors or three-dimensional structure vs. claim 9): "a semiconductor projection of the first conductivity type comprising a first side surface and a second side surface .…" does not appear verbatim in the fetched reference text. Correct the quote or treat the disclosure as unverified before relying on it.
⚠ Unverified reference quotation in claim chart (US7015078B1 — Silicon on insulator substrate having improved thermal conductivity and method of its formation vs. claim 1): "providing an SOI substrate comprising a silicon carbide thermal dissipation layer, a dielectric layer formed on the s…" does not appear verbatim in the fetched reference text. Correct the quote or treat the disclosure as unverified before relying on it.
⚠ Unverified reference quotation in claim chart (US7202517B2 — Multiple gate semiconductor device and method for forming same vs. claim 9): "The FinFET device 100 includes a semiconductor layer 102 disposed on a substrate 101 ... The substrate 101 may be a s…" does not appear verbatim in the fetched reference text. Correct the quote or treat the disclosure as unverified before relying on it.
⚠ Unverified reference quotation in claim chart (US7202517B2 — Multiple gate semiconductor device and method for forming same vs. claim 9): "The FinFET device 100 includes a source region 104 and a drain 105 region connected by a fin 106 , where the fin 106 …" does not appear verbatim in the fetched reference text. Correct the quote or treat the disclosure as unverified before relying on it.

Target Patent Summary

Title: Fin field effect transistor having a highly doped region
Technical field: FinFET (Fin field effect transistor) semiconductor devices, specifically FinFET devices with structures to mitigate hot carrier injection through effective oxide thickness engineering

Specification summary

The patent discloses a FinFET device with a non-conductive highly doped region located along multiple outer edges of a channel region in a three-dimensional fin protruding from a planar substrate. The highly doped region has a doping concentration (e.g., 1E18–1E20 cm⁻³, using boron or BF₂) high enough to prevent formation of a conduction channel in that region (non-conductive), effectively increasing the threshold voltage in the doped zone. A gate dielectric layer is located over the highly doped region, and a gate material (second fin) overlies the first fin. The non-conductive highly doped region and the gate dielectric collectively provide an increased effective oxide thickness (Eox = thickness of highly doped region + thickness of gate dielectric), which reduces the electric field across the gate oxide and mitigates hot carrier injection. The method of formation involves forming fins, performing surface implantation through a dummy gate oxide, a two-step anneal for transient enhanced diffusion to build up dopant concentration at the fin surface, followed by a replacement metal gate process.

Claims (20)

1.
INDA Fin field effect transistor (FinFET) device, comprising: a first fin of semiconducting material protruding from a semiconductor substrate, wherein the first fin of semiconducting material comprises a channel region and a highly doped region located along multiple outer edges of the channel region; a gate region protruding from the semiconductor substrate as a second fin that overlies the first fin of semiconducting material; and a gate dielectric layer located between the highly doped region and the gate region; wherein the highly doped region is vertically and laterally arranged between the channel region and the gate dielectric layer.
2.
DEP · of 1The FinFET device of claim 1, wherein the highly doped region comprises an inverted 'U' shape having two vertical segments, extending outward from a lateral segment abutting a to of the first fin of semiconducting material, along sidewalls of the first fin of semiconducting material, wherein the highly doped region is nested within the gate dielectric layer so that the highly doped region and the gate dielectric layer form concentric structures.
3.
DEP · of 2The FinFET device of claim 2, wherein the two vertical segments abut the gate dielectric layer on one side and the channel region on an opposing second side.
4.
DEP · of 1The FinFET device of claim 1, wherein the highly doped region comprises sidewalls that form planar surfaces with sidewalls of an underlying semiconductor material.
5.
DEP · of 1The FinFET device of claim 1, wherein the highly doped region has a doping concentration in a range of between approximately 1E18 cm−3 and approximately 1E20 cm−3.
6.
DEP · of 1The FinFET device of claim 1, wherein the highly doped region has a dopant species of boron (B) or borondifluoride (BF2).
7.
DEP · of 1The FinFET device of claim 1, wherein the highly doped region comprises a higher doping concentration than a bulk of the first fin of semiconducting material.
8.
DEP · of 1The FinFET device of claim 1, wherein the non conductive highly doped region has a first height that is less than a second height of the gate dielectric layer.
9.
INDA Fin field effect transistor (FinFET) device, comprising: a planar substrate comprising a semiconductor material; a channel region comprising a first fin of semiconductor material protruding from the planar substrate and extending along a first direction, wherein the first fin of semiconductor material comprises a highly doped region located along one or more outer edges of the first fin of semiconductor material; a gate region protruding from the planar substrate as a second fin that overlies the first fin of semiconductor material, wherein the gate region extends along a second direction perpendicular to the first direction; and a gate dielectric layer disposed between the highly doped region and the gate region, wherein the highly doped region extends from a to of the first fin of semiconducting material to a location that is substantially aligned with a bottom surface of the gate region.
10.
DEP · of 9The FinFET device of claim 9, wherein the highly doped region has a doping concentration in a range of between approximately 1E18 cm−3 and approximately 1E20 cm−3.
11.
DEP · of 10The FinFET device of claim 10, wherein the highly doped region has a dopant species of boron (B) or borondifluoride (BF2).
12.
DEP · of 9The FinFET device of claim 9, wherein the highly doped region is disposed within a top portion of the first fin of semiconductor material and comprises sidewalls that form planar surfaces with sidewalls of an underlying lower portion of the first fin of semiconductor material.
13.
DEP · of 9The FinFET device of claim 9, further comprising: sections of dielectric material extending along the first direction and separating the first fin of semiconductor material from additional fins of semiconductor material extending parallel to the first fin of semiconductor material.
14.
DEP · of 9The FinFET device of claim 9, wherein the highly doped region is vertically and laterally arranged between the channel region and the gate dielectric layer.
15.
INDA Fin field effect transistor (FinFET) device, comprising: a first fin of semiconducting material protruding from a top surface of a semiconductor substrate and extending along a first direction; a gate region protruding from the top surface of the semiconductor substrate as a second fin that extends along a second direction, perpendicular to the first direction, and which overlies the first fin; and a region located along a top surface and sidewalls of the first fin of semiconducting material, and having a first doping concentration that is higher than a second doping concentration of underlying sections of the first fin of semiconducting material, wherein the region is laterally disposed between source and drain regions that vertically extend to positions that are below the gate region; and a gate dielectric layer disposed between the gate region and a top surface and sidewalls of the region.
16.
DEP · of 15The FinFET device of claim 15, wherein the region has a first height that is less than a second height of the gate dielectric layer.
17.
DEP · of 15The FinFET device of claim 15, wherein the region is disposed within a top portion of the first fin of semiconducting material and comprises sidewalls that form planar surfaced with sidewalls of an underlying lower portion of the first fin of semiconducting material.
18.
DEP · of 15The FinFET device of claim 15, wherein the region comprises a same semiconductor material as the first fin of semiconducting material.
19.
DEP · of 15The FinFET device of claim 15, wherein the gate dielectric layer comprises one or more of silicon oxide (SiO2), hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2).
20.
DEP · of 15The FinFET device of claim 15, further comprising: sections of dielectric material extending along the first direction and separating the first fin from additional fins of semiconductor material.

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Constructed from the target patent’s own published language.

FinFET highly doped region channel outer edges non-conductive
FinFET fin surface doping hot carrier injection mitigation effective oxide thickness
FinFET channel doping between gate dielectric and channel region
FinFET inverted U shape doped region concentric gate dielectric
tri-gate FinFET surface implant boron BF2 threshold voltage increase
FinFET fin doping profile higher concentration surface than bulk
FinFET non-conductive doped region increases effective oxide thickness
FinFET channel implant doping 1E18 1E20 cm-3 reliability
FinFET highly doped fin region gate dielectric vertically laterally between channel
FinFET doped region sidewalls planar coplanar underlying semiconductor fin
FinFET doped region height less than gate dielectric height
FinFET source drain regions extending below gate region laterally flanking doped channel
multi-gate FinFET fin surface passivation fluorine BF2 mobility
FinFET gate structure second fin overlying first fin perpendicular