Invalidity Analysis — US9570589 (public record)

For attorney review — not a legal opinion, not a validity determination. No eligible reference anticipates any target claim: every claim chart confirms that the defining inventive sequence — selectively nitriding a top thickness portion of the fin into a semiconductor-nitride layer, removing that fin-derived nitride to form an opening between spacers, and epitaxially filling the opening with a stressor — is absent from each single reference. All viable grounds are therefore §103 combinations. The strongest candidate builds on US20140332861A1, which cleanly supplies the front-end structure (discrete fins, a recessed inter-fin insulation layer whose top is below the fin top and covers a lower sidewall portion, and nitride sidewall spacers formed by deposition and etch-back), then adds a remote-plasma nitridation reference for selective nitridation of Si over SiO2, and the FinFET strain-engineering reference for the recess-and-epitaxial-SiGe/SiC stressor motivation. The pervasive weakness across every combination is that the eligible nitridation references teach monolayer-to-ultrathin interfacial nitridation for passivation, not conversion of a controlled fin thickness into a sacrificial nitrided layer used to recess a fin — creating both a missing-element/reasonable-expectation gap and a potential teaching-away/hindsight vulnerability the patentee would press. These are candidate grounds for the attorney to evaluate, not validity determinations.

Candidate grounds for attorney evaluation, ranked strongest-first — not a validity determination. Confirm every reference date and quotation before relying on a ground.

Ground 1 — §103 obviousness

Strength: moderate
References: US20140332861A1, Reaction pathways in remote plasma nitridation of ultrathin SiO2 films, Is strain engineering scalable in FinFET era?: Teaching the old dog some new tricks
Claims: 1, 3, 6, 7
KSR rationale: (A) — MPEP § 2143

US20140332861A1 maps elements 1-4 and the sidewall-spacer element (including the deposit-and-etch-back formation of claims 6-7). The nitridation reference supplies the 'selectively nitriding a top portion of the fin' step using nitrogen-containing plasma (claim 3). Removal of the nitrided layer to form an opening, and epitaxial stressor fill of that opening, would be rendered obvious by the strain-engineering reference's express recess-and-epitaxy recommendation. Together the references would render claim 1 obvious as a combination of a known FinFET fin/STI/spacer structure, a known plasma-nitridation technique, and a known recess-then-epitaxial-stressor S/D scheme.

Motivation to combine: US20140332861A1 already discloses the full front-end FinFET structure (discrete fins on a substrate; a recessed oxide isolation region whose top is below the fin top and covers a lower sidewall portion; and nitride spacers on the fin sidewall formed by nitride deposition and reactive-ion etch-back). The strain-engineering reference expressly teaches that 'recess etch into the fin before S/D epitaxy is recommended for maximizing the gain' using SiGe/Si:C stressors, supplying a concrete PHOSITA motivation to recess the exposed fin top between spacers and epitaxially fill it with a stressor. The remote-plasma nitridation reference teaches low-temperature N2/He plasma nitridation of silicon surfaces, providing a known technique to controllably convert exposed silicon to silicon nitride. A PHOSITA combining these would predictably use plasma nitridation of the exposed fin top plus selective nitride removal as an alternative, self-limiting fin-recess method preceding the recommended epitaxial stressor fill — a combination of known elements yielding predictable results (MPEP § 2143 rationale A), with the strain reference supplying an articulated TSM.

Weakest link: The eligible nitridation reference teaches monolayer-to-ultrathin interfacial nitridation for passivation of Si-SiO2 interfaces, not conversion of a defined fin thickness into a sacrificial nitrided layer to recess a fin; there is no disclosure that plasma nitridation would consume a usable fin-recess thickness, so the reasonable expectation of success for the specific 'convert a thickness portion of the fin' limitation is contestable.

Patentee's likely counterarguments:

• The nitridation references are directed to a different problem (interface passivation / gate-dielectric nitridation) and are only monolayer-scale, so they neither teach nor make predictable the deliberate consumption of a fin thickness for recessing — a missing-element and no-reasonable-expectation argument (MPEP § 2143.02).
• Assembling the FinFET structure reference, an unrelated interfacial-nitridation study, and a strain-engineering overview to reconstruct the claimed nitridation-recess-fill sequence relies on impermissible hindsight drawn from the target patent (MPEP § 2143.01); none of the references suggests using nitridation as a fin-recess mechanism.

Ground 2 — §103 obviousness

Strength: moderate
References: US20140332861A1, Reaction pathways in remote plasma nitridation of ultrathin SiO2 films, Is strain engineering scalable in FinFET era?: Teaching the old dog some new tricks
Claims: 18, 20
KSR rationale: (A) — MPEP § 2143

Claim 18's structural elements 1-3 map to US20140332861A1; the 'stress layer ... epitaxially formed ... SiGe, SiGeB, SiC, or SiCP' element and the recess-and-fill process-of-formation language are supplied by the strain-engineering reference (SiGe and Si:C stressors with fin recess before epitaxy). The selective-nitridation/nitride-removal sub-steps are supplied by the nitridation reference. Claim 20's silicon-nitride nitrided layer and oxide/oxynitride spacer are addressed by the silicon-nitride spacer/nitridation chemistry, subject to the spacer-material mismatch noted below.

Motivation to combine: Same combination as ground 1 applied to the device claim: US20140332861A1 supplies discrete fins, a recessed insulation layer covering a lower fin sidewall portion, and nitride spacers on the upper fin sidewall; the strain-engineering reference supplies the epitaxial SiGe/Si:C (SiC/SiCP) stressor located where the fin has been recessed, expressly recommending recess etch before S/D epitaxy; the nitridation reference supplies the plasma technique for forming (and enabling selective removal of) the silicon-nitride layer by which the recess/opening is created. A PHOSITA seeking the recognized drive-current benefit of embedded stressors in FinFETs would predictably arrive at the claimed device structure (MPEP § 2143 rationale A).

Weakest link: As in ground 1, no eligible reference discloses forming the opening by selectively nitriding and removing a fin thickness portion; additionally US20140332861A1's spacers are silicon nitride, whereas claim 20 recites the sidewall spacer of silicon oxide or silicon oxynitride, requiring a further substitution not squarely supported by the cited art.

Patentee's likely counterarguments:

• The claimed device is defined by a specific process of formation (selective nitridation then removal) that no reference teaches; the strain reference discloses a conventional recess etch, not nitridation-based recessing, so the combination does not reach the claim as a whole (MPEP § 2141.02).
• US20140332861A1 uses nitride as a protective spacer and forms isolation by thermal oxidation of the fin — using nitride to consume the fin body would run counter to its principle of operation, and its nitride spacer does not meet claim 20's oxide/oxynitride spacer limitation (missing element).

Ground 3 — §103 obviousness

Strength: moderate
References: US20140332861A1, Reaction pathways in remote plasma nitridation of ultrathin SiO2 films, Monolayer-level controlled incorporation of nitrogen at Si–SiO2 interfaces using remote plasma processing, Is strain engineering scalable in FinFET era?: Teaching the old dog some new tricks
Claims: 2, 9, 10, 11, 16, 19
KSR rationale: (A) — MPEP § 2143

Claim 10's silicon fin / silicon-oxide insulation and claim 2/9/19's selective-nitridation-with-un-nitrided-insulation limitations map to the silicon-fin/oxide structure of US20140332861A1 combined with the Si-vs-SiO2 nitridation behavior discussed in the nitridation references. Claim 16's nitrogen-containing gas being N2, N2/Ar, or N2/He is directly disclosed by the remote-plasma nitridation references (N2/He and N2 plasmas). Claim 11's silicon-nitride nitrided layer follows from nitriding a silicon fin, though the oxide/oxynitride spacer material is the mismatch flagged above.

Motivation to combine: These dependent claims add material-selection and selectivity limitations. The remote-plasma nitridation references teach nitriding silicon surfaces with N2/He or N2 plasma and address the differential nitridation behavior of Si versus SiO2 (nitrogen incorporation at Si-SiO2 interfaces), which a PHOSITA would apply to select fin (silicon) and insulation (silicon oxide) materials so that the fin nitrides preferentially while the oxide remains substantially un-nitrided. Combined with the US20140332861A1 silicon-fin/silicon-oxide-isolation structure and the strain reference's stressor scheme, the material choices and selectivity are predictable design selections (MPEP § 2143 rationale A).

Weakest link: The nitridation references study nitrogen incorporation for interface/dielectric engineering and do not establish a nitridation-rate differential sufficient to leave a bulk oxide isolation layer un-nitrided while consuming a fin thickness; the 'nitriding rate greater than' and 'un-nitrided insulation' limitations rely on an inference the references do not squarely support.

Patentee's likely counterarguments:

• The cited nitridation studies concern controlled monolayer nitrogen incorporation at interfaces, the opposite regime from consuming a fin thickness while leaving isolation oxide un-nitrided; using them to prove the claimed selectivity is an inherency/expectation stretch (MPEP § 2112, § 2143.02).
• Claim 11's oxide/oxynitride spacer is not disclosed by the nitride-spacer references, so at least one dependent limitation remains missing from the combination.

Ground 4 — §103 obviousness

Strength: weak
References: US20140332861A1, High Selectivity in Dry Etching of Silicon Nitride over Si Using a Novel Hydrofluorocarbon Etch Gas in a Microwave Excited Plasma for FinFET, Reaction pathways in remote plasma nitridation of ultrathin SiO2 films, Is strain engineering scalable in FinFET era?: Teaching the old dog some new tricks
Claims: 5, 13, 14
KSR rationale: (A) — MPEP § 2143

The nitride-formation (nitridation reference) and highly selective nitride-removal (dry-etch reference) steps, both compatible with microwave plasma, would render obvious the repeated nitride/strip cycle of claim 5 and the microwave-plasma/selective-energy limitations of claims 13-14, when applied to the US20140332861A1 fin/spacer structure ahead of the strain reference's epitaxial fill.

Motivation to combine: Claim 5 recites iterating the nitride/remove cycle to deepen the opening; claims 13-14 recite microwave/inductive plasma with energy above Si-Si but below Si-O bond energy. The high-selectivity dry-etch reference teaches highly selective removal of silicon nitride over silicon in a microwave-excited plasma for FinFET, supplying the selective nitride-removal step and the microwave-plasma modality, while the nitridation reference supplies the selective-nitridation step. A PHOSITA seeking a controlled, repeatable fin recess would predictably iterate a self-limiting nitride-form/nitride-strip cycle using these known, mutually selective processes (MPEP § 2143 rationale A).

Weakest link: The dry-etch reference removes SiN by plasma etching, whereas the fin-recess concept depends on the unshown premise that plasma nitridation consumes a meaningful fin thickness per cycle; without that, the iterative deepening of claim 5 and the bond-energy-selectivity theory of claim 14 lack evidentiary support and read as post-hoc reconstruction.

Patentee's likely counterarguments:

• The energy-window limitation (greater than Si-Si, less than Si-O bond energy) of claim 14 is not quantitatively taught by any cited reference; asserting it is an unsupported inherency argument (MPEP § 2112).
• The dry-etch reference is directed to etching deposited SiN films, not to stripping a fin-derived nitrided layer in an iterative recess process, so combining it to reach claim 5 relies on hindsight (MPEP § 2143.01).

Ground 5 — §103 obviousness

Strength: weak
References: US20140332861A1, US20050186742A1, Reaction pathways in remote plasma nitridation of ultrathin SiO2 films, Is strain engineering scalable in FinFET era?: Teaching the old dog some new tricks
Claims: 8
KSR rationale: (A) — MPEP § 2143

The primary combination (ground 1) supplies claim 1; US20050186742A1 supplies the conventional gate-across-fin-on-insulation structure recited in claim 8, integrated in the normal process sequence before spacer formation.

Motivation to combine: Claim 8 adds forming a gate structure across a length portion of the fin and on the insulation layer prior to forming the spacers. US20050186742A1 (and US7151018B1) disclose a conventional FinFET gate electrode formed across the fin on the isolation/insulation layer with sidewall spacers, which is the standard architecture into which the nitridation-recess-and-stressor source/drain flow of the primary combination would be integrated. A PHOSITA would predictably form the gate before defining spacer-bounded source/drain openings, per ordinary FinFET process order (MPEP § 2143 rationale A).

Weakest link: This ground inherits ground 1's core deficiency (no reference teaches nitridation-based fin recess); the added gate reference only supplies a conventional element and does not cure that central gap.

Patentee's likely counterarguments:

• Adding a conventional gate reference does not remedy the absence of the claimed selective-nitridation-to-stressor core in any reference; the combination as a whole still fails to reach claim 1 from which claim 8 depends (MPEP § 2141.02).
• The gate references are directed to salicidation/contact-area architectures with different processing goals, and combining them with interfacial-nitridation studies to reconstruct the claim is hindsight-driven (MPEP § 2143.01).

Ground 6 — §103 obviousness

Strength: weak
References: US20140332861A1, Reaction pathways in remote plasma nitridation of ultrathin SiO2 films, Monolayer-level controlled incorporation of nitrogen at Si–SiO2 interfaces using remote plasma processing, Is strain engineering scalable in FinFET era?: Teaching the old dog some new tricks
Claims: 12, 15
KSR rationale: (E) — MPEP § 2143

The recited pressure and microwave-nitridation parameter ranges would be rendered obvious as routine optimization of the known plasma-nitridation conditions taught by the nitridation references, applied within the primary combination's fin-recess-and-stressor flow.

Motivation to combine: Claims 12 and 15 recite specific nitridation process windows (pressure ~0.1-20 Torr; microwave N2 flow ~50-500 sccm, ~300-500°C, ~1-10 Torr, source power ≤1000 W). The remote-plasma nitridation references disclose low-temperature N2/He and N2 plasma nitridation of silicon in overlapping low-pressure/low-temperature regimes, and optimizing flow, pressure, temperature, and power within known plasma-nitridation ranges is routine result-effective-variable optimization from a finite set of predictable operating conditions (MPEP § 2143 rationale E).

Weakest link: The eligible references do not disclose the specific microwave-nitridation parameter set of claim 15 (N2 flow, temperature, pressure, and ≤1000 W power for fin-thickness nitridation); asserting these numeric windows as routine optimization without a reference disclosing comparable fin-nitridation conditions is a thin optimization argument.

Patentee's likely counterarguments:

• There is no reference disclosing nitridation of a fin at these specific conditions to consume a fin thickness; treating the ranges as result-effective variables presupposes the very fin-recess-by-nitridation process that no reference teaches (MPEP § 2145).
• The nitridation references target ultrathin interface nitridation, so their process windows are not shown to be applicable to, or predictive of success for, the claimed fin-thickness conversion (MPEP § 2143.02).

Unverified leads (no established date — not usable as grounds)

These references had no establishable date, so they were withheld from the grounds analysis — an undated reference cannot anchor a §102/§103 ground. Undated web results are often post-priority commentary describing the target’s own commercialized feature; treat these strictly as leads to date manually.

• Growth of Si3N4 Thin Films on Si(111) Surface by RF-N2 Plasma Nitriding (non-patent literature)
• Process Development of Sidewall Spacer Features for sub-300nm Dense Silicon FinFETs (non-patent literature)
• Channel Stress Engineering Through Source/Drain Recess Optimization and Its Process Variation Study for 5 nm-node FinFETs | IEEE Conference Publication | IEEE Xplore (non-patent literature)

Element-by-element mapping of the strongest prior-art references against the target’s independent claims. A single absent element defeats §102 anticipation for that reference (it may still contribute to a §103 combination). Quoted reference passages are verified verbatim against the fetched reference text; any unverified quote is flagged in the Priority-Date Discipline section. For attorney review.

US6960509B1 — Method of fabricating three dimensional gate structure using oxygen diffusion vs. claim 1

Verdict: missing element(s) — no §102.

For attorney review — not a legal opinion, not a validity determination. US6960509B1 maps cleanly onto only the first claim element (forming discrete silicon fins on a substrate, per claim 21 and the Abstract), and arguably part of element 2 to the extent it discloses a silicon dioxide substrate/layer associated with the fins — though it does not disclose a recessed insulation layer between discrete fins with a top surface lower than the fin covering a portion of the fin sidewall (elements 3-4). The reference is fundamentally directed to OXIDATION to thin a fin, not NITRIDATION: its process converts silicon to silicon dioxide (element 6 is absent — no selective nitriding, no semiconductor nitride layer) and then wet-etches that oxide away to expose a thinned fin rather than to form an opening between spacers (element 7 absent). Critically, the reference discloses no sidewall spacer (element 5 absent) and no stress layer filling any opening (element 8 absent). Because at least five limitations are absent from this single reference, it would NOT anticipate claim 1 under §102 (MPEP § 2131 requires every element arranged as in the claim). The oxidation-vs-nitridation mismatch, the absence of a sidewall spacer, and the absence of a stress-layer fill are the dispositive missing links; this reference could at most be a candidate secondary reference in a §103 analysis, and the patentee's strongest counterargument is that the reference teaches the opposite chemistry (oxide formation for fin-thinning) with no motivation to create a recessed opening for a stressor.

US6960509B1 — Method of fabricating three dimensional gate structure using oxygen diffusion vs. claim 18

Verdict: missing element(s) — no §102.

US6960509B1 maps only weakly onto claim 18. It discloses a silicon fin on a silicon dioxide substrate (element 1) and an underlying silicon dioxide layer (element 2, at most partially — the reference describes an SOI-type buried oxide/substrate, not a recessed insulation layer between discrete fins whose top surface is lower than the fin top and covers a portion of the fin sidewall, so the specific recessed-insulation geometry is unverified). Every remaining, defining limitation of claim 18 is ABSENT from the reference: there is no sidewall spacer (much less one with a top surface higher than the fin top), no stress layer, and critically the reference's process is OXYGEN DIFFUSION/OXIDATION to convert silicon to silicon dioxide to shrink the fin — not the claimed SELECTIVE NITRIDATION to form a semiconductor nitride layer, its removal to form an opening, and epitaxial filling of that opening with a SiGe/SiGeB/SiC/SiCP stress layer. Because multiple limitations (elements 3–9) are missing from this single reference, it would NOT anticipate claim 18 under §102 (MPEP § 2131). Note also that as a method-of-fabrication reference it does not describe the finished device structure of claim 18; the oxide-vs-nitride distinction is the cleanest dispositive gap. The reference could at most be considered as a background fin-formation teaching in a §103 analysis, but on its own text it lacks the stress-layer and nitridation core of the claim.

US7151018B1 — Method and apparatus for transistor sidewall salicidation vs. claim 1

Verdict: missing element(s) — no §102.

US7151018B1 shares only the general FinFET context with claim 1: it discloses source/drain fins on an SOI/buried-oxide substrate and dielectric spacers (nitride/oxide/oxynitride) alongside a gate electrode, which map partially to the 'discrete fins,' 'insulation layer on the substrate,' and 'sidewall spacer' elements. However, the reference's stated purpose is entirely different — it forms a self-aligned metal salicide on exposed silicon sidewalls by palladium activation and electroless metal deposition followed by anneal. It provides NO disclosure of the three core limitations that define the target claim's process: (6) selectively nitriding the fin top to convert a set thickness into a semiconductor nitride layer, (7) removing that nitrided layer to form an opening between adjacent spacers, and (8) filling the opening with a stress layer. Additionally, the reference does not disclose a recessed insulation layer whose top surface is lower than the fin top and which covers a portion of the fin sidewall (elements 3 and 4); its 'insulator' is a buried oxide beneath the fins, not a between-fin STI recessed along the fin sidewall. Because at least five limitations — including the three most distinctive nitridation/removal/stress-fill steps — are absent from this single reference, it would NOT anticipate claim 1 under §102. This is a candidate analysis for the attorney's evaluation; the reference could at most contribute background FinFET/spacer context to a §103 combination, not an anticipation ground.

US7151018B1 — Method and apparatus for transistor sidewall salicidation vs. claim 18

Verdict: missing element(s) — no §102.

US7151018B1 discloses only the general FinFET architecture — discrete source/drain fins on a substrate (element 1, disclosed), a buried-oxide insulator (element 2, only partially disclosed because the reference's oxide lies beneath the fins as an SOI buried layer and is never described as an inter-fin insulation layer having a top surface lower than the fin top that covers a portion of the fin sidewall), and sidewall spacers (element 3, only partially disclosed because the spacers 110/112 are described as flanking the gate electrode, not as covering the fin sidewall with a top surface higher than the fin top). Critically, the entire stress-layer subject matter of claim 18 is absent: the reference is directed to forming a metal salicide by electroless deposition and annealing, and contains no disclosure of a stress layer (element 4), selective nitriding of the fin top into a nitrided layer (element 5), removing that nitrided layer to form an opening (element 6), filling the opening with a stress layer (element 7), epitaxial formation (element 8), or SiGe/SiGeB/SiC/SiCP stressor material (element 9). Because multiple limitations — including the core stress-layer/selective-nitridation sequence — are entirely missing from this single reference, it would not anticipate claim 18 under §102 (MPEP § 2131); at most it evidences the generic FinFET context and could figure only in a §103 combination the attorney may wish to evaluate.

US7560344B2 — Semiconductor device having a pair of fins and method of manufacturing the same vs. claim 1

Verdict: missing element(s) — no §102.

US7560344B2 discloses forming discrete fins on a substrate (fins 105a/105b) and an insulating device separation layer 130 that covers the lower external portion of the fins to a controlled height, which maps at least partially to the fin-formation and recessed-insulation-layer limitations. Its inner/upper spacer insulating layers arguably read in part on the 'sidewall spacer' limitation, though the reference forms inner spacers to define a void rather than spacers that cover a fin sidewall while exposing its top for an epitaxial fill — so this element is only partially supported. Critically, the reference is entirely silent on the three core process steps of claim 1: (6) selectively nitriding a top portion of the fin to form a semiconductor nitride layer, (7) removing that nitrided layer to create an opening between adjacent spacers, and (8) filling that opening with a stress layer. The reference instead describes a non-volatile fin memory device using thermal oxidation, void formation, and gate/storage-node layers — no nitridation-based fin recess and no stress layer. Because at least these three limitations are absent from this single reference, it would NOT anticipate claim 1 under §102 (MPEP § 2131); the missing steps cannot be supplied by combining other references within a §102 analysis. The reference may, at most, be a candidate secondary reference for a §103 combination for the fin/insulation/spacer structural limitations. This is candidate prior-art analysis for attorney review, not a legal opinion or validity determination.

US7560344B2 — Semiconductor device having a pair of fins and method of manufacturing the same vs. claim 18

Verdict: missing element(s) — no §102.

The reference cleanly maps the basic FinFET structural framework of claim 18: it discloses discrete fins protruding from a body/substrate (fins 105a/105b), and it discloses insulating layers between/around the fins (device separation layer 130 covering the lower external sidewall, and inner/upper spacer insulating layers 135/155) that can be read on the recited 'insulation layer' and 'sidewall spacer,' though only partially — the reference does not expressly establish that the spacer top surface is 'higher than the top surface of the fin' as claimed. Critically, however, the reference is entirely silent on the entire stress-layer subsystem that forms the heart of claim 18: there is NO stress layer on the top of the fin, NO selective nitridation of a fin top portion into a semiconductor-nitride layer, NO removal of that nitrided layer to form an opening, and NO epitaxial SiGe/SiGeB/SiC/SiCP stressor filling that opening (this reference is a non-volatile fin memory device defining a void and storage-node layer, not a source/drain stressor device). Because at least six claim limitations (elements 4–9) are wholly absent from this single reference, it does not anticipate claim 18 under §102 (MPEP § 2131); the missing limitations cannot be cured by combination within a §102 analysis, though the reference may still contribute to a §103 combination for the structural fin/spacer framework only.

US20050186742A1 — Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same vs. claim 1

Verdict: missing element(s) — no §102.

This reference is a device/method disclosure for vertical-channel FinFETs with enlarged source/drain contact area, and it maps cleanly only onto the front-end structural elements of claim 1: forming discrete fins on a substrate (claim 15), forming a device isolation/insulation layer between/adjacent the fins (claims 10, 15, 20), and recessing that isolation layer so it sits below the fin top while covering a lower sidewall portion (claim 15). Those three isolation-related elements are at best partially disclosed because the reference frames the isolation layer around the gate/channel geometry rather than the recited recessed-below-fin-top spacer-fill flow. Critically, the reference is ABSENT as to the core inventive sequence of claim 1: it discloses no sidewall spacer covering the fin sidewall while exposing the fin top (its spacers are on the gate-electrode sidewalls, per claims 6, 23-25), no selective nitriding of the fin top to form a semiconductor-nitride layer, no removal of a nitrided layer to form an opening, and no stress layer filling that opening — the reference instead teaches thermal oxidation and source/drain contact formation (claims 14, 16). Because at least four independent limitations (elements 5-8) are absent from this single reference, it does not anticipate claim 1 under §102/MPEP § 2131; the reference could at most serve as a base for a §103 combination addressing the fin/isolation architecture, with the nitridation-and-stressor steps needing to come from other art. This is candidate prior-art analysis for attorney review, not a legal opinion or validity determination.

US20050186742A1 — Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same vs. claim 18

Verdict: missing element(s) — no §102.

The reference discloses a bulk-substrate FinFET architecture whose fin and recessed device-isolation features map to the first two structural limitations of claim 18: element (1) (discrete fins on a substrate) is expressly disclosed ('forming a fin-shaped active region vertically protruding from a semiconductor substrate'), and element (2) (recessed insulation layer covering a lower sidewall portion of the fin) is partially disclosed via the 'device isolation layer adjacent sidewalls of the fin-shaped active region' that is 'recess[ed]... to expose upper surfaces and sidewalls' of the fin. However, the reference is silent on the dispositive core of claim 18: element (3)'s sidewall spacer covering the FIN sidewall with a top higher than the fin (the reference's spacers are on gate-electrode sidewalls, not fin sidewalls), and elements (4)-(9) — the stress layer, the selective-nitridation/nitride-removal process by which the opening is formed, the epitaxial fill, and the SiGe/SiGeB/SiC/SiCP material — appear nowhere in the provided text (the reference instead forms metal source/drain contacts). Because multiple limitations are absent from this single reference, it would NOT anticipate claim 18 under §102 (MPEP § 2131); it may at most be a component of a §103 combination, which is outside the scope of an anticipation chart. This is candidate prior-art analysis for attorney review, not a legal opinion or validity determination.

US20140332861A1 — Fin structure with varying isolation thickness vs. claim 1

Verdict: missing element(s) — no §102.

For attorney review — not a legal opinion, not a validity determination. The reference maps cleanly onto the front-end structural elements of claim 1: discrete fins on a substrate (claim 16), a recessed oxide/insulation region between the fins whose top surface sits below the fin top (claims 1, 6, 12), and nitride spacers formed on the fin sidewalls (claim 1). However, the reference is fundamentally directed to creating isolation regions of varying thickness by thermal OXIDATION of the fin base, not to source/drain stressor formation. Three dispositive limitations are absent: (element 6) the reference forms nitride spacers by DEPOSITION of a nitride layer and etch-back, and never selectively NITRIDES the fin itself to convert a top thickness portion of the fin into a nitrided layer on a remainder fin — its only fin-consuming reaction is thermal oxidation beneath the fin; (element 7) there is no removal of a fin-derived nitride layer to form an opening on the remainder fin between adjacent spacers; and (element 8) there is no stress layer of any kind, epitaxial or otherwise, filling any opening. Because at least these three limitations are missing from this single reference, it would NOT anticipate claim 1 under §102 (MPEP § 2131 — every element must be present and arranged as in the claim). The reference could at most be a §103 building block for the fin/insulation/spacer preamble features, but the selective-nitridation-to-stressor core of the claim is not disclosed here.

US20140332861A1 — Fin structure with varying isolation thickness vs. claim 18

Verdict: missing element(s) — no §102.

The reference discloses the structural front end of claim 18 — discrete fins on a semiconductor substrate (claim 16), a recessed oxide/insulation region whose top lies below the fin top and covers a lower sidewall portion (claims 6, 12), and nitride spacers on the upper fin sidewalls (claims 1, 20). However, the spacer's 'top surface higher than the top surface of the fin' limitation is only partially supported (the reference recites spacers on an 'upper sidewall portion' without establishing a top higher than the fin top), so it is flagged partial pending verification against the reference's figures, which were not provided. Critically, the entire stress-layer subject matter — elements 4 through 9 (a stress layer on the fin top between spacers, formed by selectively nitriding the fin top into a nitrided layer, removing that layer to form an opening, and epitaxially filling the opening with SiGe/SiGeB/SiC/SiCP) — is wholly ABSENT. The reference uses nitride as a protective spacer and forms isolation by THERMAL OXIDATION of the fin, not by nitriding the fin body, and it contains no epitaxial stressor of any kind. Because multiple limitations are absent, this single reference would NOT anticipate claim 18 under §102 (MPEP § 2131); no inherency argument cures a missing epitaxial-stressor element. The reference could at most serve as one component of a §103 combination, which requires a separate motivation-to-combine analysis. For attorney review — not a legal opinion, not a validity determination.